The simulation time in conventional full chip functional tests can take days or weeks in existing silicon on chip (hereafter SOC) products. The length of the simulation time typically depends on (i) the test duration; (ii) the target electronic device; and (iii) the number of active electronic components with the electronic device.
In addition, as computer systems continue to develop, there are increasing timing differences that occur between registered transfer level (hereafter RTL) models and actual silicon. These increasing timing differences cause additional debug time and other time delays that inhibit high volume manufacturing (hereafter HVM) of developing SOCs. The additional debug time and other time delays directly affect product ramps and time to market (TTM).
Modern functional testing emulators might address some of the delay issues associated with HVM of developing SOCs. However, such emulators are usually expensive to maintain and are typically incapable of addressing issues stemming from the RTL vs. silicon timing differences.